Ultra-high Speed A/D Converters Using Zero-crossing-based Circuits

With an increasing need for higher data rates, both wireless applications and data links are demanding higher speed analog-todigital converters (ADC) with medium resolution. In particular, this work will investigate ADC’s with sampling rate up to 10 Gs/s with 6-8 bits of resolution. Time-interleaved converters achieve their high sampling rate by placing several converters in parallel. Each individual converter, or channel, has a delayed sampling clock and operates at a reduced sampling rate. Therefore each channel is responsible for digitizing a different time slice. This method requires that the individual converters, which make up the parallel combination, be matched. Mismatches and non-idealities, such as gain error, timing error, and voltage offset, degrade the performance. Therefore channel matching is an important design consideration for time-interleaved ADCs.